Synchronous dynamic random access memory (SDRAM) components are used in the system memory of many modern computer systems, particularly desktop machines. In the SDRAM design, a starting address received from a memory controller is stored in an address register within the SDRAM. After the SDRAM is read or written at the starting address, the starting address is automatically incremented in response to a DRAM clock signal to address successive memory locations. Because successive addresses are generated within the DRAM component rather than being received over a relatively high capacitance address bus, each incremental address becomes valid more quickly than it could otherwise be received from the memory controller. Consequently, data can be read from or written to sequential addresses in SDRAM significantly faster than in other types of memory. Because data flow in modern computer systems often involves transferring blocks of data to or from sequential addresses in system memory (e.g., to fill cache lines, transfer streams of video data, etc.), the fast access to sequential SDRAM locations usually translates into a faster overall access rate for SDRAM than for other types of memory.
Despite the performance advantages of SDRAM, extended-data-out (EDO) DRAM remains prevalent in mobile devices, such as notebook and laptop computers. The primary reason for this is that SDRAM typically consumes more power than EDO DRAM, a precious commodity in battery-operated machines. For example, when in an idle state (i.e., no access initiated or in progress), SDRAM components may consume as much as fifty times more power than idle EDO DRAM components.
One technique for reducing the power consumed by SDRAM-based system memory is to place the system memory in a power-down mode by deasserting a clock enable signal that is supplied to each SDRAM component in the system memory. When the clock enable signal is deasserted, logic elements within the individual DRAM components no longer change state in response to the DRAM clock signal. Because the greatest power draw occurs as the DRAM logic elements transition between states, deasserting the clock enable signal dramatically reduces the power consumed by idle SDRAM components, making them comparable, at least from a power consumption standpoint, to idle EDO DRAM components.
One disadvantage of powering down the system memory is that it must be re-powered each time access to system memory is required. This presents at least two problems. First, SDRAM cannot be instantly transitioned between power down and powered states so that a timing penalty is incurred for each re-powering of the system memory. While this timing penalty is usually short (one or two DRAM clock cycles, for example), it can become significant when the system memory is frequently switched between the power-down and powered states. A second and related problem is that at least some portion of system memory is typically in use whenever a computer-user is actively using the computer system. Thus, when power saving is most critical, i.e., when the computer system is turned on and being used by the computer-user, it is often impractical to power the system memory down. What is needed is a way to reduce system memory power consumption without having to power the entire system memory down.